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1 features ? single voltage read/write operation: 2.65v to 3.6v access time ? 70 ns sector erase architecture ? fifteen 32k word (64k bytes) sectors with individual write lockout ? eight 4k word (8k bytes) sectors with individual write lockout fast byte/word program time ? 12 s fast sector erase time ? 300 ms suspend/resume feature for erase and program ? supports reading and programming from any sector by suspending erase of a different sector ? supports reading any byte/word in the non-suspending sectors by suspending programming of any other byte/word low-power operation ?12 ma active ? 13 a standby data polling, toggle bit, ready/busy for end of program detection reset input for device initialization sector lockdown support tsop and cbga package options top or bottom boot block configuration available 128-bit protection register minimum 100,000 erase cycles common flash interface (cfi) description the at49bv802a(t) is a 2.7-volt 8-megabit flash memory organized as 524,288 words of 16 bits each or 1,048,576 bytes of 8 bits each. the x16 data appears on i/o0 - i/o15; the x8 data appears on i/o0 - i/o7. the memory is divided into 23 sectors for erase operations. the at49bv802a(t) is offered in a 48-lead tsop and a 48-ball cbga package. the device has ce and oe control signals to avoid any bus conten- tion. this device can be read or reprogrammed using a single power supply, making it ideally suited for in-system programming. pin configurations pin name function a0 - a18 addresses ce chip enable oe output enable we write enable reset reset rdy/busy ready/busy output i/o0 - i/o14 data inputs/outputs i/o15 (a-1) i/o15 (data input/output, word mode) a-1 (lsb address input, byte mode) byte selects byte or word mode nc no connect 8-megabit (512k x 16/ 1m x 8) 3-volt only flash memory at49bv802a at49bv802at rev. 3405c?flash?9/04
2 at49bv802a(t) 3405c?flash?9/04 tsop top view type 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 nc nc we reset nc nc rdy/busy a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte gnd i/o15/a-1 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 vcc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe gnd ce a0 cbga top view (ball down) a b c d e f g h 1 23456 rdy/busy nc a18 nc i/o2 i/o10 i/o11 i/o3 a3 a4 a2 a1 a0 ce oe vss a7 a17 a6 a5 i/o0 i/o8 i/o9 i/o1 we rst nc nc i/o5 i/o12 vcc i/o4 a9 a8 a10 a11 i/o7 i/o14 i/o13 i/o6 a13 a12 a14 a15 a16 byte i/015/a-1 vss the device powers on in the read mode. command sequences are used to place the device in other operation modes such as program and eras e. the device has the capability to protect the data in any sector (see ?sector lockdown? section). to increase the flexibility of the device, it contains an erase suspend and program suspend feature. this feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the memory. the end of a program or an erase cycle is detected by the ready/busy pin, data polling or by the toggle bit. a six-byte command (enter single pulse program mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. after entering the six-byte code, only single pulses on the write control lines are required for writing into the device. this mode (single pulse byte/word program) is exited by powering down the device, or by pulsing the reset pin low for a minimum of 500 ns and then bringing it back to v cc . erase, erase suspend/resume and program suspend/resume commands will not work while in this mode; if entered they will result in data being programmed into the device. it is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code. the byte pin controls whether the device data i/o pins operate in the byte or word configura- tion. if the byte pin is set at logic ?1?, the device is in word configuration, i/o0 - i/o15 are active and controlled by ce and oe . if the byte pin is set at logic ?0?, the device is in byte configuration, and only data i/o pins i/o0 - i/o7 are active and controlled by ce and oe . the data i/o pins i/o8 - i/o14 are tri- stated, and the i/o15 pin is used as an input for the lsb (a-1) address function.
3 at49bv802a(t) 3405c?flash?9/04 block diagram device operation read: the at49bv802a(t) is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins are asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus contention. command sequences: when the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. in order to perform other device functions, a series of command sequences are entered into the device. the command sequences are shown in the ?command definition in hex? table on page 11 (i/o8 - i/o15 are don?t care inputs for the command codes). the command sequences are written by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . standard microprocessor write timings are used. the address locations used in the command sequences ar e not affected by entering the command sequences. reset: a reset input pin is provided to ease some system applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset input halts the present device operation and puts the outputs of the device in a high impedance state. when a high level is reasserted on the reset pin, the device returns to the read or standby mode, depending upon the state of the control inputs. erasure: before a byte/word can be reprogrammed, it must be erased. the erased state of memory bits is a logical ?1?. the entire dev ice can be erased by using the chip erase com- mand or individual sectors can be erased by using the sector erase command. identifier register status register data comparator output multiplexer output buffer input buffer command register data register y-gating write state machine program/erase voltage switch ce we oe reset byte rdy/busy vcc gnd y-decoder x-decoder input buffer address latch i/o0 - i/o15/a-1 a0 - a18 main memory
4 at49bv802a(t) 3405c?flash?9/04 chip erase: the entire device can be erased at one ti me by using the six-byte chip erase software code. after the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. the maximum time to erase the chip is t ec . if the sector lockdown has been enabled, the chip erase will not erase the data in the sector that has been locked out; it will erase only the unpr otected sectors. after the chip erase, the device will return to the read or standby mode. sector erase: as an alternative to a full chip erase, the device is organized into 23 sec- tors (sa0 - sa22) that can be individually erased. the sector erase command is a six-bus cycle operation. the sector address is latched on the falling we edge of the sixth cycle while the 30h data input command is latched on the rising edge of we . the sector erase starts after the rising edge of we of the sixth cycle. the erase operatio n is internally controlled; it will automatically time to completion. the maximum time to erase a sector is t sec . when the sec- tor programming lockdown feature is not enabled, the sector will erase (from the same sector erase command). an attempt to erase a sector that has been protected will result in the oper- ation terminating immediately. byte/word programming: once a memory block is erased, it is programmed (to a logi- cal ?0?) on a byte-by-byte or on a word-by-word basis. programming is accomplished via the internal device command register and is a four-bus cycle operation. the device will automati- cally generate the required internal program pulses. any commands written to the chip during the embedded programming cycle will be ignored. if a hardware reset happens during programming, the data at the location being programmed will be corrupted. please note that a data ?0? cannot be programmed back to a ?1?; only erase operations can convert ?0?s to ?1?s. programming is completed after the specified t bp cycle time. the data polling feature or the toggle bit feature may be used to indicate the end of a program cycle. if the erase/program status bit is a ?1?, the device was not able to verify that the erase or program operation was performed successfully. program/erase status: the device provides several bits to determine the status of a program or erase operation: i/o2, i/o5, i/o6 and i/o7. the ?status bit table? on page 10 and the following four sections describe the function of these bits. to provide greater flexibility for system designers, the at49bv802a(t) contains a programmable configuration register. the configuration register allows the user to specify the status bit operation. the configuration reg- ister can be set to one of two different values, ?00? or ?01?. if the configuration register is set to ?00?, the part will automatically return to the read mode after a successful program or erase operation. if the configuration register is set to a ?01?, a product id exit command must be given after a successful program or erase oper ation before the part will return to the read mode. it is important to note that whether the configuration register is set to a ?00? or to a ?01?, any unsuccessful program or erase operation requires using the product id exit command to return the device to read mode. the default value (after power-up) for the configuration regis- ter is ?00?. using the four-bus cycle set conf iguration register command as shown in the ?command definition in hex? table on page 11, the value of the configuration register can be changed. voltages applied to the reset pin will not alter the value of the configuration regis- ter. the value of the configuration register will affect the operation of the i/o7 status bit as described below.
5 at49bv802a(t) 3405c?flash?9/04 data polling: the at49bv802a(t) features data polling to indicate the end of a program cycle. if the status configuration register is set to a ?00?, during a program cycle an attempted read of the last byte/word loaded will result in the complement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. during a chip or sector erase operation, an attempt to read the device will give a ?0? on i/o7. once the program or erase cycle has completed, true data will be read from the device. data polling may begin at any time during the program cycle. please see ?status bit table? on page 10 for more details. if the status bit configuration register is set to a ?01?, the i/o7 status bit will be low while the device is actively programming or erasing dat a. i/o7 will go high when the device has com- pleted a program or erase operation. once i/o7 has gone high, status information on the other pins can be checked. the data polling status bit must be used in conjunction with the erase/program and v pp status bit as shown in the algorithm in figures 1 and 2 on page 8. toggle bit: in addition to data polling the at49bv802a(t) provides another method for determining the end of a program or erase cycle. during a program or erase operation, suc- cessive attempts to read data from the memory will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. please see ?sta- tus bit table? on page 10 for more details. the toggle bit status bit should be used in conjunction with the erase/program status bit as shown in the algorithm in figures 3 and 4 on page 9. erase/program status bit: the device offers a status bit on i/o5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. if the status bit is a ?1?, the device is unable to verify that an erase or a byte/word program oper- ation has been successfully performed. if a program (sector erase) command is issued to a protected sector, the protected sector will not be programmed (erased). the device will go to a status read mode and the i/o5 status bit will be set high, indicating the program (erase) opera- tion did not complete as requested. once the erase/program status bit has been set to a ?1?, the system must write the product id exit command to return to the read mode. the erase/program status bit is a ?0? while the erase or program operation is still in progress. please see ?status bit table? on page 10 for more details. sector lockdown: each sector has a programming lockdown feature. this feature pre- vents programming of data in the designated sectors once the feature has been enabled. these sectors can contain secure code that is used to bring up the system. enabling the lock- down feature will allow the boot code to stay in the device while data in the rest of the device is updated. this feature does not have to be activated; any sector?s usage as a write-protected region is optional to the user. at power-up or reset, all sectors are unlocked. to activate the lockdown for a specific sector, the six-bus cycle sector lockdown command must be issued. once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed. sector lockdown detection: a software method is available to determine if program- ming of a sector is locked down. when the devic e is in the software product identification mode (see ?software product identification entry/exit? sections on page 22), a read from address location 00002h within a sector will show if programming the sector is locked down. if the data on i/o0 is low, the sector can be programmed; if the data on i/o0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. the software product identification exit code should be used to return to standard operation.
6 at49bv802a(t) 3405c?flash?9/04 sector lockdown override: the only way to unlock a sector that is locked down is through reset or power-up cycles. after power-up or reset, the content of a sector that is locked down can be erased and reprogrammed. erase suspend/erase resume: the erase suspend command allows the system to interrupt a sector or chip erase operation and then program or read data from a different sector within the memory. after the erase suspend co mmand is given, the device requires a maxi- mum time of 15 s to suspend the erase operation. after the erase operation has been suspended, the system can then read data or progr am data to any other sector within the device. an address is not required during the erase suspend command. during a sector erase suspend, another sector cannot be erased. to resume the sector erase operation, the system must write the erase resume command. the erase resume command is a one-bus cycle command. the device also supports an erase su spend during a complete chip erase. while the chip erase is suspended, the user can read from any sector within the memory that is pro- tected. the command sequence for a chip erase suspend and a sector erase suspend are the same. program suspend/program resume: the program suspend command allows the system to interrupt a programming operation and then read data from a different byte/word within the memory. after the program suspend command is given, the device requires a max- imum of 20 s to suspend the programming operation. after the programming operation has been suspended, the system can then read data from any other byte/word that is not con- tained in the sector in which the programming operation was suspended. an address is not required during the program suspend operation. to resume the programming operation, the system must write the program resume command. the program suspend and resume are one-bus cycle commands. the command sequence for the erase suspend and program sus- pend are the same, and the command sequence for the erase resume and program resume are the same. product identification: the product identification mode identifies the device and man- ufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the atmel product. for details, see ?operating modes? on page 15 (for hardware operation) or ?software product identification entry/exit? sections on page 22. the manufacturer and device codes are the same for both modes. 128-bit protection register: the at49bv802a(t) contains a 128-bit register that can be used for security purposes in system design. the protection register is divided into two 64- bit blocks. the two blocks are designated as block a and block b. the data in block a is non-changeable and is programmed at the factory with a unique number. the data in block b is programmed by the user and can be locked out such that data in the block cannot be repro- grammed. to program block b in the protection register, the four-bus cycle program protection register command must be used as shown in the ?command definition in hex? table on page 11. to lock out block b, the four-bus cycle lock protection register command must be used as shown in the ?command definition in hex? table. data bit d1 must be zero during the fourth bus cycle. all other data bits during the fourth bus cycle are don?t cares. to determine whether block b is locked out, the product id entry command is given followed by a read operation from address 80h. if data bit d1 is zero, block b is locked. if data bit d1 is one, block b can be reprogrammed. please see the ?protection register addressing table? on page 12 for the address locations in the protection register. to read the protection register, the product id entry command is given followed by a normal read operation from an address within the protection register. after determining whether block b is protected or not, or reading the protection register, the product id exit command must be given prior to performing any other operation.
7 at49bv802a(t) 3405c?flash?9/04 rdy/busy : an open-drain ready/busy output pin provides another method of detecting the end of a program or erase operation. rdy/busy is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. the open-drain con- nection allows for or-tying of several devices to the same rdy/busy line. please see ?status bit table? on page 10 for more details. cfi: common flash interface (cfi) is a published, standardized data structure that may be read from a flash device. cfi allows system software to query the installed device to deter- mine the configurations, various electrical and timing parameters, and functions supported by the device. cfi is used to allow the system to learn how to interface to the flash device most optimally. the two primary benefits of using cfi are ease of upgrading and second source availability. the command to enter the cfi query mode is a one-bus cycle command which requires writing data 98h to address 55h. the cfi query command can be written when the device is ready to read data or can also be written when the part is in the product id mode. once in the cfi query mode, the system can read cfi data at the addresses given in table 1 on page 23. to exit the cfi query mode, the product id exit command must be given. hardware data protection: the hardware data protection feature protects against inadvertent programs to the at49bv802a(t) in the following ways: (a) v cc sense: if v cc is below 1.8v (typical), the program function is inhibited. (b) v cc power-on delay: once v cc has reached the v cc sense level, the device will automatically time out 10 ms (typical) before pro- gramming. (c) program inhibit: holding any one of oe low, ce high or we high inhibits program cycles. input levels: while operating with a 2.65v to 3.6v power supply, the address inputs and control inputs (oe , ce and we ) may be driven from 0 to 5.5v without adversely affecting the operation of the device. the i/o lines can only be driven from 0 to v cc + 0.6v.
8 at49bv802a(t) 3405c?flash?9/04 figure 1. data polling algorithm (configuration register = 00) notes: 1. va = valid address for programming. during a sec- tor erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. i/o7 should be rechecked even if i/o5 = ?1? because i/o7 may change simultaneously with i/o5. start read i/o7 - i/o0 addr = va i/o7 = data? i/o5 = 1? read i/o7 - i/o0 addr = va i/o7 = data? program/erase operation not successful, write product id exit command no no no yes yes yes program/erase operation successful, device in read mode figure 2. data polling algorithm (configuration register = 01) note: 1. va = valid address for programming. during a sec- tor erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful, write product id exit command no no no yes yes yes
9 at49bv802a(t) 3405c?flash?9/04 figure 3. toggle bit algorithm (configuration register = 00) note: 1. the system should recheck the toggle bit even if i/o5 = ?1? because the toggle bit may stop toggling as i/o5 changes to ?1?. start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful, device in read mode no no no yes yes yes figure 4. toggle bit algorithm (configuration register = 01) note: 1. the system should recheck the toggle bit even if i/o5 = ?1? because the toggle bit may stop toggling as i/o5 changes to ?1?. start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful, write product id exit command no no no yes yes yes
10 at49bv802a(t) 3405c?flash?9/04 notes: 1. i/o5 switches to a ?1? when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. status bit table status bit i/o7 i/o7 i/o6 i/o5 (1) i/o2 rdy/busy configuration register 00 01 00/01 00/01 00/01 00/01 programming i/o7 0 toggle 0 1 0 erasing 0 0 toggle 0 toggle 0 erase suspended & read erasing sector 1110toggle1 erase suspended & read non-erasing sector data data data data data 1 erase suspended & program non-erasing sector i/o7 0 toggle 0 toggle 0 erase suspended & program suspended and reading from non-suspended sectors data data data data data 1 program suspended & read programming sector i/o7 1 1 0 toggle 1 program suspended & read non-programming sector data data data data data 1
11 at49bv802a(t) 3405c?flash?9/04 notes: 1. the data format shown for each bus cycle is as follows; i/o7 - i/o0 (hex). in word operation i/o15 - i/o8 are don?t care. the address format shown for each bus cycle is as follows: a11 - a0 (hex). address a18 through a11 are don?t ca re in the word mode. address a18 through a11 and a-1 are don?t care in the byte mode. 2. since a11 is a don?t care, aaa can be replaced with 2aa. 3. sa = sector address. any byte/word address within a sector c an be used to designate the sector address (see pages 13 - 14 for details). 4. once a sector is in the lockdown mode, data in the protecte d sector cannot be changed unless the chip is reset or power cycle d. 5. either one of the product id exit commands can be used. 6. if data bit d1 is ?0?, block b is locked. if data bit d1 is ?1?, block b can be reprogrammed. 7. the default state (after power-up) of the configuration register is ?00?. 8. bytes of data other than f0 may be used to exit the product id mode. however, it is recommended that f0 be used. command definition in hex (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 555 aa aaa (2) 55 555 80 555 aa aaa 55 555 10 sector erase 6 555 aa aaa 55 555 80 555 aa aaa 55 sa (3)(4) 30 byte/word program 4 555 aa aaa 55 555 a0 addr d in enter single pulse program mode 6 555 aa aaa 55 555 80 555 aa aaa 55 555 a0 single pulse byte/word program 1addrd in sector lockdown 6 555 aa aaa (2) 55 555 80 555 aa aaa 55 sa (3)(4) 60 erase/program suspend 1 xxx b0 erase/program resume 1 xxx 30 product id entry 3 555 aa aaa 55 555 90 product id exit (5) 3 555 aa aaa 55 555 f0 (8) product id exit (5) 1 xxx f0 (8) program protection register 4 555 aa aaa 55 555 c0 addr d in lock protection register - block b 4 555 aa aaa 55 555 c0 080 x0 status of block b protection 4 555 aa aaa 55 555 90 80 d out (6) set configuration register 4 555 aa aaa 55 555 d0 xxx 00/01 (7) cfi query 1 x55 98 absolute maximum ratings* temperature under bias ................................ -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on v pp with respect to ground ...................................-0.6v to +13.0v
12 at49bv802a(t) 3405c?flash?9/04 note: all address lines not specified in the above table must be ?0? when accessing the protection register, i.e., a18 - a8 = 0. protection register addressing table word use block a7 a6 a5 a4 a3 a2 a1 a0 0 factory a 10000001 1 factory a 10000010 2 factory a 10000011 3 factory a 10000100 4 user b 10000101 5 user b 10000110 6 user b 10000111 7 user b 10001000
13 at49bv802a(t) 3405c?flash?9/04 at49bv802a ? sector address table sector size (bytes/words) x8 address range (a18 - a-1) x16 address range (a18 - a0) sa0 8k/4k 000000 - 001fff 00000 - 00fff sa1 8k/4k 002000 - 003fff 01000 - 01fff sa2 8k/4k 004000 - 005fff 02000 - 02fff sa3 8k/4k 006000 - 007fff 03000 - 03fff sa4 8k/4k 008000 - 009fff 04000 - 04fff sa5 8k/4k 00a000 - 00bfff 05000 - 05fff sa6 8k/4k 00c000 - 00dfff 06000 - 06fff sa7 8k/4k 00e000 - 00ffff 07000 - 07fff sa8 64k/32k 010000 - 01ffff 08000 - 0ffff sa9 64k/32k 020000 - 02ffff 10000 - 17fff sa10 64k/32k 030000 - 03ffff 18000 - 1ffff sa11 64k/32k 040000 - 04ffff 20000 - 27fff sa12 64k/32k 050000 - 05ffff 28000 - 2ffff sa13 64k/32k 060000 - 06ffff 30000 - 37fff sa14 64k/32k 070000 - 07ffff 38000 - 3ffff sa15 64k/32k 080000 - 08ffff 40000 - 47fff sa16 64k/32k 090000 - 09ffff 48000 - 4ffff sa17 64k/32k 0a0000 - 0affff 50000 - 57fff sa18 64k/32k 0b0000 - 0bffff 58000 - 5ffff sa19 64k/32k 0c0000 - 0cffff 60000 - 67fff sa20 64k/32k 0d0000 - 0dffff 68000 - 6ffff sa21 64k/32k 0e0000 - 0effff 70000 - 77fff sa22 64k/32k 0f0000 - 0fffff 78000 - 7ffff
14 at49bv802a(t) 3405c?flash?9/04 at49bv802at ? sector address table sector size (bytes/words) x8 address range (a18 - a-1) x16 address range (a18 - a0) sa0 64k/32k 000000 - 00ffff 00000 - 07fff sa1 64k/32k 010000 - 01ffff 08000 - 0ffff sa2 64k/32k 020000 - 02ffff 10000 - 17fff sa3 64k/32k 030000 - 03ffff 18000 - 1ffff sa4 64k/32k 040000 - 04ffff 20000 - 27fff sa5 64k/32k 050000 - 05ffff 28000 - 2ffff sa6 64k/32k 060000 - 06ffff 30000 - 37fff sa7 64k/32k 070000 - 07ffff 38000 - 3ffff sa8 64k/32k 080000 - 08ffff 40000 - 47fff sa9 64k/32k 090000 - 09ffff 48000 - 4ffff sa10 64k/32k 0a0000 - 0affff 50000 - 57fff sa11 64k/32k 0b0000 - 0bffff 58000 - 5ffff sa12 64k/32k 0c0000 - 0cffff 60000 - 67fff sa13 64k/32k 0d0000 - 0dffff 68000 - 6ffff sa14 64k/32k 0e0000 - 0effff 70000 - 77fff sa15 8k/4k 0f0000 - 0f1fff 78000 - 78fff sa16 8k/4k f20000 - f3ffff 79000 - 79fff sa17 8k/4k f40000 - f5ffff 7a000 - 7afff sa18 8k/4k f60000 - f7ffff 7b000 - 7bfff sa19 8k/4k f80000 - f9ffff 7c000 - 7cfff sa20 8k/4k fa0000 - fbffff 7d000 - 7dfff sa21 8k/4k fc0000 - fdffff 7e000 - 7efff sa22 8k/4k fe0000 - ffffff 7f000 - 7ffff
15 at49bv802a(t) 3405c?flash?9/04 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms on page 20. 3. v h = 12.0v 0.5v. 4. manufacturer code: 1fh (x8); 001fh (x16), device code: 00c1h - at49bv802a; 00c3h - at49bv802at. 5. see details under ?software product identification entry/exit? on page 22. dc and ac operating range at49bv802a(t)-70 operating temperature (case) ind. -40c - 85c v cc power supply 2.65v to 3.6v operating modes mode ce oe we reset ai i/o read v il v il v ih v ih ai d out program/erase (2) v il v ih v il v ih ai d in standby/program inhibit v ih x (1) xv ih x high-z program inhibit xxv ih v ih xv il xv ih output disable x v ih xv ih high-z reset xxx v il x high-z product identification hardware v il v il v ih v ih a1 - a18 = v il , a9 = v h (3) , a0 = v il manufacturer code (4) a1 - a18 = v il , a9 = v h (3) , a0 = v ih device code (4) software (5) v ih a0 = v il , a1 - a18 = v il manufacturer code (4) a0 = v ih , a1 - a18 = v il device code (4)
16 at49bv802a(t) 3405c?flash?9/04 note: 1. in the erase mode, i cc is 45 ma. dc characteristics symbol parameter condition min typ max units i li input load current v in = 0v to v cc 2a i lo output leakage current v i/o = 0v to v cc 10 a i sb v cc standby current cmos ce = v cc - 0.3v to v cc 13 25 a i cc (1) v cc active read current f = 5 mhz; i out = 0 ma 12 25 ma i cc1 v cc programming current 40 ma v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol1 output low voltage i ol = 2.1 ma 0.45 v v ol2 output low voltage i ol = 1.0 ma 0.20 v v oh1 output high voltage i oh = -400 a 2.4 v v oh2 output high voltage i oh = -100 a 2.5 v
17 at49bv802a(t) 3405c?flash?9/04 ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce , whichever occurs first (cl = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read characteristics symbol parameter at49bv802a(t)-70 units min max t rc read cycle time 70 ns t acc address to output delay 70 ns t ce (1) ce to output delay 70 ns t oe (2) oe to output delay 0 20 ns t df (3)(4) ce or oe to output float 0 25 ns t oh output hold from oe , ce or address, whichever occurred first 0ns t ro reset to output delay 100 ns output valid output high z reset oe t oe t ce address valid t df t oh t acc t ro ce address t rc
18 at49bv802a(t) 3405c?flash?9/04 input test waveforms and measurement level t r , t f < 5 ns output test load note: this parameter is characterized and is not 100% tested. pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
19 at49bv802a(t) 3405c?flash?9/04 ac byte/word load waveforms we controlled ce controlled ac byte/word load characteristics symbol parameter min max units t as , t oes address, oe setup time 0 ns t ah address hold time 35 ns t cs chip select setup time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )35ns t ds data setup time 35 ns t dh , t oeh data, oe hold time 0 ns t wph write pulse width high 35 ns
20 at49bv802a(t) 3405c?flash?9/04 program cycle waveforms sector or chip erase cycle waveforms notes: 1. oe must be high only when we and ce are both low. 2. for chip erase, the address should be 555. for sector erase, the address depends on what sector is to be erased. (see note 3 under ?command definitions in hex? on page 11.) 3. for chip erase, the data should be 10h, and for sector erase, the data should be 30h. program cycle characteristics symbol parameter min typ max units t bp byte/word programming time 12 200 s t as address setup time 0ns t ah address hold time 35 ns t ds data setup time 35 ns t dh data hold time 0ns t wp write pulse width 35 ns t wph write pulse width high 35 ns t wc write cycle time 70 ns t rp reset pulse width 500 ns t ec chip erase cycle time 13 seconds t sec1 sector erase cycle time (4k word sectors) 0.3 3.0 seconds t sec2 sector erase cycle time (32k word sectors) 1.0 5.0 seconds t es erase suspend time 15 s t ps program suspend time 10 s oe program cycle input data address a0 55 555 555 aa aaa t bp t wph t wp ce we a0 - a18 data t as t ah t dh t ds 555 aa t wc oe (1) aa 80 note 3 55 55 555 555 note 2 aa word 0 word 1 word 2 word 3 word 4 word 5 aaa aaa t wph t wp ce we a0-a18 data t as t ah t ec t dh t ds 555 t wc
21 at49bv802a(t) 3405c?flash?9/04 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ?ac read characteristics? on page 17. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ?ac read characteristics? on page 17. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns a0-a18 we ce oe i/o7 t dh t oeh t oe high z an an an an an t wr toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 50 ns t wr write recovery time 0 ns
22 at49bv802a(t) 3405c?flash?9/04 software product identification entry (1) software product identification exit (1)(6) notes: 1. data format: i/o15 - i/o8 (don?t care); i/o7 - i/o0 (hex) address format: a11 - a0 (hex), a-1, and a11 - a18 (don?t care). 2. a1 - a18 = v il . manufacturer code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code: 1fh(x8); 001fh(x16) device code: 00c1h - at49bv802a; 00c3h - at49bv802at. 6. either one of the product id exit commands can be used. load data aa to address 555 load data 55 to address aaa load data 90 to address 555 enter product identification mode (2)(3)(5) load data aa to address 555 load data 55 to address aaa load data f0 to address 555 exit product identification mode (4) or load data f0 to any address exit product identification mode (4) sector lockdown enable algorithm (1) notes: 1. data format: i/o15 - i/o8 (don?t care); i/o7 - i/o0 (hex) address format: a11 - a0 (hex), a-1, and a11 - a18 (don?t care). 2. sector lockdown feature enabled. load data aa to address 555 load data 55 to address aaa load data 80 to address 555 load data aa to address 555 load data 55 to address aaa load data 60 to sector address pause 200 s (2)
23 at49bv802a(t) 3405c?flash?9/04 table 1. common flash interface definition for at49bv802a(t) address [x16 mode] address [x8 mode] data comments 10h 20h 0051h ?q? 11h 22h 0052h ?r? 12h 24h 0059h ?y? 13h 26h 0002h 14h 28h 0000h 15h 2ah 0041h 16h 2ch 0000h 17h 2eh 0000h 18h 30h 0000h 19h 32h 0000h 1ah 34h 0000h 1bh 36h 0027h v cc min write/erase 1ch 38h 0036h v cc max write/erase 1dh 3ah 0000h v pp min voltage ? no v pp 1eh 3ch 0000h v pp max voltage ? no v pp 1fh 3eh 0004h typ word write ? 12 s 20h 40h 0000h 21h 42h 000ah typ block erase: 1,000 ms 22h 44h 000eh typ chip erase: 13,000 ms 23h 46h 0004h max word write/typ time 24h 48h 0000h n/a 25h 4ah 0002h max block erase/typ block erase 26h 4ch 0002h max chip erase/typ chip erase 27h 4eh 0014h device size 28h 50h 0002h x8/x16 device 29h 52h 0000h x8/x16 device 2ah 54h 0000h multiple byte write not supported 2bh 56h 0000h multiple byte write not supported 2ch 58h 0002h 2 regions, x = 2 2dh 5ah 000eh 64k bytes, y = 14 2eh 5ch 0000h 64k bytes, y = 14 2fh 5eh 0000h 64k bytes, z = 256 30h 60h 0001h 64k bytes, z = 256 31h 62h 0007h 8k bytes, y = 7 32h 64h 0000h 8k bytes, y = 7 33h 66h 0020h 8k bytes, z = 32 34h 68h 0000h 8k bytes, z = 32
24 at49bv802a(t) 3405c?flash?9/04 vendor specific extended query 41h 82h 0050h ?p? 42h 84h 0052h ?r? 43h 86h 0049h ?i? 44h 88h 0031h major version number, ascii 45h 8ah 0030h minor version number, ascii 46h 8ch 0087h bit 0 ? chip erase supported, 0 ? no, 1 ? yes bit 1 ? erase suspend supported, 0 ? no, 1 ? yes bit 2 ? program suspend supported, 0 ? no, 1 ? yes bit 3 ? simultaneous operations supported, 0 ? no, 1 ? yes bit 4 ? burst mode read supported, 0 ? no, 1 ? yes bit 5 ? page mode read supported, 0 ? no, 1 ? yes bit 6 ? queued erase supported, 0 ? no, 1 ? yes bit 7 ? protection bits supported, 0 ? no, 1 ? yes 47h 8eh 0000h (top) or 0001h (bottom) bit 8 ? top (?0?) or bottom (?1?) boot block device undefined bits are ?0? 48h 90h 0000h bit 0 ? 4-word linear burst with wrap around, 0 ? no, 1 ? yes bit 1 ? 8-word linear burst with wrap around, 0 ? no, 1 ? yes bit 2 ? continuos burst, 0 ? no, 1 ? yes undefined bits are ?0? 49h 92h 0000h bit 0 ? 4-word page, 0 ? no, 1 ? yes bit 1 ? 8-word page, 0 ? no, 1 ? yes undefined bits are ?0? 4ah 94h 0080h location of protection register lock byte, the section?s first byte 4bh 96h 0003h # of bytes in the factory prog section of prot register ? 2*n 4ch 98h 0003h # of bytes in the user prog section of prot register ? 2*n table 1. common flash interface definition for at49bv802a(t) (continued) address [x16 mode] address [x8 mode] data comments
25 at49bv802a(t) 3405c?flash?9/04 at49bv802a(t) ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 70 25 0.025 AT49BV802A-70CI at49bv802a-70ti 48c19 48t industrial (-40 to 85 c) 70 25 0.025 at49bv802at-70ci at49bv802at-70ti 48c19 48t industrial (-40 to 85 c) package type 48c19 48-ball, plastic chip-size ball grid array package (cbga) 48t 48-lead, plastic thin small outline package (tsop)
26 at49bv802a(t) 3405c?flash?9/04 packaging information 48c19 ? cbga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 48c19 , 48-ball (6 x 8 array), 0.80 mm pitch, 6.0 x 8.0 x 1.0 mm chip-scale ball grid array package (cbga) a 48c19 7/2/03 top view bottom view side view a b c d e f g h 1.0 ref 1.20 ref e d a1 ball id 6 54321 e1 d1 a a1 e e a1 ball corner ? b common dimensions (unit of measure = mm) symbol min nom max note e 5.90 6.00 6.10 e1 4.0 typ d 7.90 8.00 8.10 d1 5.6 typ a ? ? 1.0 a1 0.22 ? ? e 0.80 bsc ? b 0.40 typ
27 at49bv802a(t) 3405c?flash?9/04 48t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 48t , 48-lead (12 x 20 mm package) plastic thin small outline package, type i (tsop) b 48t 10/18/01 pin 1 0o ~ 8o d1 d pin 1 identifier b e e a a2 c l gage plane seating plane l1 a1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation dd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 11.90 12.00 12.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
28 at49bv802a(t) 3405c?flash?9/04 revision history summary revision a ? february 2004 ? initial release revision b ? march 2004 ? removed at49bv808a(t) device from datasheet ? modified cbga pinout and package drawing for at49bv802a(t) revision c ? september 2004 ? removed preliminary from the datasheet
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